1. Field of the Invention
The present invention relates to an ESD protection circuit, and particularly relates to an ESD protection circuit, which can isolate a pad and internal circuit to prevent formation of a parasitic NPN channel.
2. Description of the Prior Art
FIG. 1 illustrates a prior art ESD protection circuit 100. As shown in FIG. 1, the ESD protection circuit includes a first rectifying element 101, a second rectifying element 103, and a resistor 105. The first rectifying element 101 and the second rectifying element 103 can be a MOS (metal-oxide semiconductor) FET or a diode. The ESD protection circuit 100 is coupled to a pad 107 and an internal circuit 109 to prevent an ESD pulse being transmitted from the pad 107 to the internal circuit 109. Normally, the ESD pulse will be transmitted out via the first rectifying element 101 or the second rectifying element 103. If the resistor 105 is too small, however, a current transmitting through the resistor 105 will enter the internal circuit 109, thereby damaging it. The internal circuit can be easier to protect if the resistor 105 is larger, but this may cause circuit delay, which is a disadvantage for high-speed operation.
FIG. 2 illustrates a prior art ESD circuit 200, which is used to prevent a current entering the internal circuit 217. As shown in FIG. 2, the ESD protection circuit 200 comprises a transmitting gate circuit 201 and a control circuit 203, a first rectifying element 219 and a second rectifying element 221. The control circuit 203 is used for controlling the operation of the transmitting gate circuit 201. The transmitting gate circuit 201 is turned on (conductive) when in a normal operation mode, and the transmitting gate circuit 201 turns off to prevent the ESD pulse from entering an inner circuit. The size of the transmitting gate circuit 201 can be adjusted to adjust the input resistance of the pad 205. The capacitor 207 and the resistor 209 of the control circuit 203 constitute a delay circuit to determine the turning on and turning off time of the transmitting gate circuit 201. The N MOSFETs 211 and 213 are used for providing a biasing voltage to the P-Well or body of the N MOSFET 215 and the N-Well of the P MOSFET 214 respectively. The first rectifying element 219 and the second rectifying element 221 can be a MOS (metal-oxide semiconductor) FET or a diode.
However, since the P MOSFET 214 is directly coupled to the capacitor 207 and the resistor 209, the gate voltage of the P MOSFET 214 is generated via the ESD pulse coupling to the capacitor 207 when an ESD pulse enters, thus the P MOSFET 214 may not turn off completely. Besides, the N MOSFET 213 may have a parasitic NPN path due to improper layout, thus a destructive ESD pulse may transmit through the NPN path, damaging the parasitic NPN, if the ESD pulse transmits from pad 205 to the second voltage level VGND. Therefore, the ESD protection circuit 200 may lose its function of protection.
U.S. Pat. No. 7,009,826 also discloses an oscillating circuit utilized as an ESD protection circuit. Such a circuit does not provide perfect isolation to an RF circuit and pad, however. Furthermore, the circuit co-utilizes an LC oscillating circuit, it may have an increased area, and may have unnecessary oscillation when in a normal operation. Other related operations of the circuit are disclosed in U.S. Pat. No. 7,009,826, and therefore omitted here for brevity.
Therefore, a new invention is needed to solve these problems.